ASIC

ETH Zurich is one of the leading universities in the world in designing their own Application Specific Integrated Circuits (ASIC). The Chip Gallery contains information on more than 450 ASICs that were designed at ETH Zurich with considerable support from Microelectronics Design Center. On average 10 to 20 ASICs are designed and tested at the ETH Zurich every year. Roughly half of these designs are student IC design projects, where students visiting the VLSI series of lectures are given the opportunity to design their own digital ASICs (since 2015 using a 65nm technology) as part of a semester thesis and later test their own designs on an industrial Advantest SoC V93000 IC tester. The design center supports this effort by providing the necessary design flow, giving lectures and preparing exercises for the VLSI Lecture series.

Services

The Microelectronic Design Center will help you:

• Understand if an ASIC is the right solution for you, how you can design it, what technology and tools to use for the design
• Evaluate realistic performances of solutions if/when implemented as an integrated circuit. These can be used in publications to compare to state of art.
• Have access to the design flows and tools/licenses needed for the design
• Review your designs, make suggestions
• Establish the connection to the manufacturers, help you with chip finishing problems.
• Develop test strategies for your integrated circuits
• Opportunities available to start-up companies of ETH that are thinking of designing their own ASICs

Manufacturing your designs

We use Multi-Project Wafer (MPW) services for prototype quantities (usually 10-100 chips) that share the costs between multiple participants. Depending on the technology (feature size in nm), special capabilities (SOI, high voltage) and circuit area the prices will vary greatly. It is possible to get a chip manufactured for as little as 5'000 CHF.

We have access to many different providers (TSMC, UMC, Globalfoundries, ST Microelectronics, SMIC, AMS, X-Fab and others) through different MPW service providers listed below. Contact us for more details.

• external pageEuropracticecall_made (IMEC/Fraunhofer)
• external pageCMPcall_made
• external pageMosiscall_made

Links

• Chip gallery: A gallery that contains most of the chips designed at ETH Zurich in the last 30 years
• EDA Wiki: Our solution database, links to technical information (ETH internal access only)